1. Field of the Invention
This invention relates generally to the replacement of defective memory cells in a semiconductor memory, and, more particularly, to the replacement of defective memory cells having the same address within a portion of the semiconductor memory.
2. Description of the Related Art
A semiconductor memory device typically includes an array of memory cells, and the array is normally divided into a number of sub-arrays. Memory cells in the array are selected for reading and writing by means of row and column address signals input to the semiconductor memory device. The row and column address signals are processed by address decoding circuitry to select row lines and column lines in the array to access the desired memory cell or memory cells. A common practice in semiconductor memory devices is to implement the decoding at more than one level. For example, a first level decoding may yield data from a plurality of memory cells in the array, while a second level of decoding will select one memory cell, or a subset of memory cells, from the plurality. Thus, an address input to a semiconductor memory device will commonly result in the selection of a plurality of memory cells in the array or sub-array of the memory device, at least at a first level of decoding. That is, a plurality of memory cells will typically be selected by, or respond to, any particular address.
When semiconductor devices are manufactured, defective memory cells may occur in the memory array or in a sub-array. To salvage the semiconductor memory device despite these defective memory cells, and thus to increase overall yield in the manufacturing process, redundancy is commonly implemented. Redundant memory elements are located throughout the memory array, and each sub-array in the memory array will typically have associated with it a plurality of redundant memory elements. When a defective memory cell is detected in a sub-array, redundant decoding circuitry associated with the redundant memory elements for that sub-array may be programmed to respond to the address of the defective memory cell. When the address of the defective memory cell is input to the sub-array, the redundant memory element will respond in place of the defective memory cell. Redundancy and its implementation is known to those of ordinary skill in the art.
In many instances, a sub-array in a memory array will be further divided such that a given address applied to the sub-array will select a plurality of memory cells in that sub-array; that is, a plurality of memory cells in the sub-array will respond to a single address. Conventional redundancy circuitry and techniques may be used to replace a plurality of defective memory cells in the sub-array if each of the defective memory cells corresponds to a unique address. In that circumstance, each of the redundant decoders may be programmed with the address corresponding to one of the defective memory cells. However, if two or more of the defective memory cells in a sub-array respond to the same address, conventional redundancy circuitry and techniques may not be used because programming a redundant address decoder to respond to the address of interest will result in the redundant memory element associated with that redundant address decoder attempting to replace two distinct memory cells in the sub-array.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.